Semiconductor integrated circuits are typically fabricated by a layering process in which several layers of material are fabricated on or in a surface of a wafer, or alternatively, on a surface of a previous layer. This fabrication process typically requires subsequent layers to be fabricated upon a smooth, planar surface of a previous layer. However, the surface topography of layers may be uneven due to an uneven topography associated with an underlying layer. As a result, a layer may need to be polished in order to present a smooth, planar surface for a subsequent processing step. For example, a layer may need to be polished prior to formation of a conductor layer or pattern on an outer surface of the layer.
In general, a semiconductor wafer may be polished to remove high topography and surface defects such as crystal lattice damage, scratches, roughness, or embedded particles of dirt or dust. The polishing process typically is accomplished with a polishing system that includes top and bottom platens (e.g. a polishing table and a wafer carrier or holder), between which the semiconductor wafer is positioned. The platens are moved relative to each other thereby causing material to be removed from the surface of the wafer. This polishing process is often referred to as mechanical planarization (MP) and is utilized to improve the quality and reliability of semiconductor devices. The polishing process may also involve the introduction of a chemical slurry to facilitate higher removal rates, along with the selective removal of materials fabricated on the semiconductor wafer. This polishing process is often referred to as chemical mechanical planarization or chemical mechanical polishing (CMP).
In these polishing processes, it is often important to determine an endpoint of the polishing process. Overpolishing (removing too much) of a conductive layer results in increased circuit resistance and potential scrapping of the semiconductor wafer. Since many processing steps have occurred prior to the polishing process, scrapping a semiconductor wafer during fabrication may undesirably result in significant financial loss. Underpolishing (removing too little) of a conductive layer on the other hand leads to failure in isolating circuits and results in electrical shorts. Presence of such electrical shorts leads to rework (redoing the CMP process) thereby disadvantageously increasing costs (e.g. production costs) associated with the semiconductor wafer. Thus, a precise endpoint detection technique is needed.
A typical method employed for determining the endpoint in polishing systems is to measure the amount of time needed to planarize a first wafer, and thereafter polishing the remaining wafers for a similar amount of time. In practice this method is extremely time consuming since machine operators must inspect each wafer after polishing. In particular, it is extremely difficult to precisely control the removal rate of material since the removal rate may vary during the polishing of an individual wafer. Moreover, the removal rate may be diminished in the process of polishing a number of wafers in sequence.
Thus, a continuing need exists for a method and an apparatus which accurately and efficiently detects when a polishing system polishes a semiconductor device down to a polishing endpoint layer.